The present invention relates to a semiconductor integrated circuit device, or in particular to a technique for mounting a large-capacity memory and a logic circuit on the same chip.
The references cited in this specification are listed below and will be referred to with the reference numbers attached thereto: Reference 1, xe2x80x9cVery Large Scale Integration Memoryxe2x80x9d by Kiyoo Itoh, published by Baifukan Co., Ltd., 1994, pp. 13, and Reference 2, JP-A-62-226494 (corresponding to U.S. Pat. No. 4,803,664).
In recent years, the importance of a system-on-chip LSI having mounted thereon both a dynamic random access memory (DRAM) and a logic circuit at the same time has increased for multimedia applications. In the future, it will become necessary to mount a DRAM, a static random access memory (SRAM) and a processor or the like on a single chip. With the conventional DRAM memory cell configured with a transistor and a special large-capacity capacitor, however, the process for fabricating the capacitor is so complicated that it is difficult to fabricate the DRAM through the same process as the logic circuit in a system-on-chip LSI. The result is a limited cost reduction. Thus a DRAM memory cell free of a capacitor is required.
Candidates are the 4.5, 3.5, 3.5 and 2.5 line-type 3-transistor cells shown in FIGS. 1.0(a) to (d) on page 13 of Reference 1, for example, which the present inventors have begun to re-evaulate. The 3-transistor transistor cell comprises a storage MOSFET for storing an information voltage in the gate thereof, a write MOSFET for writing the information voltage in the aforementioned gate, and a read MOSFET for reading the state of the aforementioned gate voltage. The 3-transistor cell, which can be easily fabricated with substantially the same process as the logic circuit, may be fabricated at low cost. Also, this cell itself has an amplification function, and therefore the operation is stable as a large read signal voltage is read on a data line. Further, this cell is suitably operated at low voltage and therefore can be implemented with low power consumption constituting a suitable application to multimedia. These features have been discovered by the present inventors.
The DRAM comprising the 3-transistor cell is described also in Reference 2. This memory has a pair of data lines and is accessible for write and read operation at high speed. In view of the fact that the information stored in the memory cell is detected and amplified by a sense amplifier, however, a dummy cell is required for each pair of the data lines, thereby requiring a correspondingly increased space. Also, the dummy cell disclosed in the cited Reference 2 has an amplification function, and therefore the reference voltage appearing on the data lines undesirably changes with time. As a result, it is difficult to set the start timing of the sense amplifier and in some cases, the read information cannot be detected by the sense amplifier. This is by reason of the fact that an excessively slow setting of the start timing of the sense amplifier reduces the differential voltage between the pair of the lines and makes unstable the operation.
Accordingly, an object of the present invention is to provide a memory not including a dummy cell.
A typical example of the present invention will be described. The dummy cell is eliminated by setting a different precharge voltage for each of the data lines making up the data line pair connected to memory cells having the amplification function. Also, the stable operation is secured by setting the reference voltage appearing on the data lines to a predetermined value. A specific example of the memory cell having the amplification function is so-called the 3-transistor cell including three transistors.